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* Copyright (C) 2011, 2013 Renesas Electronics Corporation. All rights reserved.
***********************************************************************************************************************/

/***********************************************************************************************************************
* File Name    : r_cg_dmac.h
* Version      : CodeGenerator for RL78/G13 V2.00.00.07 [22 Feb 2013]
* Device(s)    : R5F100LE
* Tool-Chain   : CA78K0R
* Description  : This file implements device driver for DMAC module.
* Creation Date: 2015-4-5
***********************************************************************************************************************/

#ifndef DMAC_H
#define DMAC_H

/***********************************************************************************************************************
Macro definitions (Register bit)
***********************************************************************************************************************/
/*
    DMA Mode Control Register n (DMCn)
*/
/* Setting of DMA transfer start software trigger (STGn) */
#define _00_DMA_TRIGGER_OPERATION_NO        (0x00U) /* no trigger operation */
#define _80_DMA_TRIGGER_OPERATION_SOFTWARE  (0x80U) /* DMA transfer is started when DMA operation is enabled */
/* Selection of DMA transfer direction (DRSn) */
#define _00_DMA_TRANSFER_DIR_SFR2RAM        (0x00U) /* SFR to internal RAM  */
#define _40_DMA_TRANSFER_DIR_RAM2SFR        (0x40U) /* internal RAM to SFR */
/* Specification of transfer data size for DMA transfer (DSn) */
#define _00_DMA_DATA_SIZE_8                 (0x00U) /* 8 bits */
#define _20_DMA_DATA_SIZE_16                (0x20U) /* 16 bits */
/* Pending of DMA transfer(DWAITn) */
#define _00_DMA_PENDING_NOTHELD             (0x00U) /* executes DMA transfer upon DMA start request */
#define _10_DMA_PENDING_HOLDS               (0x10U) /* hold DMA start request pending if any */
/* Selection of DMA stat source (IFCn3 - IFCn0) */
#define _00_DMA_TRIGGER_SOFTWARE            (0x00U) /* disable DMA transfer by interrupt */
#define _01_DMA_TRIGGER_AD                  (0x01U) /* A/D conversion end interrupt */
#define _02_DMA_TRIGGER_TM00                (0x02U) /* timer channel 0 interrupt */
#define _03_DMA_TRIGGER_TM01                (0x03U) /* timer channel 1 interrupt */
#define _04_DMA_TRIGGER_TM02                (0x04U) /* timer channel 2 interrupt */
#define _05_DMA_TRIGGER_TM03                (0x05U) /* timer channel 3 interrupt */
#define _06_DMA_TRIGGER_ST0_CSI00           (0x06U) /* UART0 transmission end / CSI00 transfer end */
#define _07_DMA_TRIGGER_SR0_CSI01           (0x07U) /* UART0 reception end / CSI01 transfer end */
#define _08_DMA_TRIGGER_ST1_CSI10           (0x08U) /* UART1 transmission end / CSI10 transfer end */
#define _09_DMA_TRIGGER_SR1_CSI11           (0x09U) /* UART1 reception end / CSI11 transfer end */
#define _0A_DMA_TRIGGER_ST2_CSI20           (0x0AU) /* UART2 transmission end / CSI20 transfer end */
#define _0B_DMA_TRIGGER_SR2_CSI21           (0x0BU) /* UART2 reception end / CSI21 transfer end */

/*
    DMA operation control register n (DRCn)
*/
/* DMA operation enable flag (DENn) */
#define _80_DMA_OPERATION_ENABLE            (0x80U) /* enable operation of DMA */
#define _00_DMA_OPERATION_DISABLE           (0x00U) /* disable operation of DMA */ 
/* DMA transfer mode flag (DSTn) */
#define _01_DMA_TRANSFER_UNDEREXEC          (0x01U) /* DMA transfer is not completed */ 
#define _00_DMA_TRANSFER_COMPLETED          (0x00U) /* DMA transfer is completed */

/***********************************************************************************************************************
Macro definitions
***********************************************************************************************************************/
#define _12_DMA1_SFR_ADDRESS                (0x12U)
#define _EFEA_DMA1_RAM_ADDRESS              (0xEFEAU)
#define _0020_DMA1_BYTE_COUNT               (0x0020U)

/***********************************************************************************************************************
Typedef definitions
***********************************************************************************************************************/

/***********************************************************************************************************************
Global functions
***********************************************************************************************************************/
void R_DMAC1_Create(void);
void R_DMAC1_Start(void);
void R_DMAC1_Stop(void);

/* Start user code for function. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
#endif
